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release date: november, 1998 order number: 273002-004 the 87C196LB may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are documented in this specification update. 87C196LB specification update
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, o r infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising fro m future changes to them. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 11/4/98 *third-party brands and names are the property of their respective owners.
87C196LB specification update 273002-004 november, 1998 iii contents revision history .................................................................................1 preface ..................................................................................................2 summary table of changes ...........................................................4 identification information ............................................................6 errata .....................................................................................................7 specification changes ...................................................................12 specification clarifications ......................................................13 documentation changes ...............................................................14

87C196LB specification update 273002-004 november, 1998 1 of 16 revision history rev. date version description 11/3/98 004 added documentation changes 3 and 4 . 08/07/98 003 added errata 3 and errata 4 , specification change 1 , and documentation changes 1 and 2 . 04/07/97 002 added errata 2 . 02/03/97 001 this is the new specification update document. it contains all identified errata published prior to this date.
87C196LB specification update 2 of 16 november, 1998 273002-004 preface as of july, 1996, intel has consolidated available historical device and documentation errata into this document type called the specification update. we have endeavored to include all documented errata in the consolidation process, however, we make no repre- sentations or warranties concerning the completeness of the specification update. this document is an update to the specifications contained in the affected documents/related documents table below. this document is a compilation of device and documentation errata, specification clarifications and changes. it is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. information types defined in nomenclature are consolidated into the specification update and are no longer published in other documents. this document may also contain information that was not previously published. nomenclature errata are design defects or errors. these may cause the published (component, board, system) behavior to deviate from published specifications. hardware and software designed to be used with any component, board, and system must consider all errata documented. specification changes are modifications to the current published specifications. these changes will be incorporated in any new release of the specification. specification clarifications describe a specification in greater detail or further highlight a specifications impact to a complex design situation. these clarifications will be incorpo- rated in any new release of the specification. documentation changes include typos, errors, or omissions from the current published specifications. these will be incorporated in any new release of the specification. affected documents/related documents title order # 87c196lx supplement to 8xc196kx, 8xc196jx, 87c196ca users manual 272973 87C196LB-20 mhz chmos 16-bit microcontroller datasheet 272807
87C196LB specification update 273002-004 november, 1998 3 of 16 note: errata remain in the specification update throughout the products lifecycle, or until a particular stepping is no longer commercially available. under these circumstances, errata removed from the specification update are archived and available upon request. specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).
87C196LB specification update 4 of 16 november, 1998 273002-004 summary table of changes the following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the 87C196LB product. intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. this table uses the following notations: codes used in summary table stepping x: errata exists in the stepping indicated. specification change or clarification that applies to this stepping. (no mark) or (blank box): this erratum is fixed in listed stepping or specification change does not apply to listed stepping. page (page): page location of item in this document. status doc: document change or update will be implemented. fix: this erratum is intended to be fixed in a future step of the com- ponent. fixed: this erratum has been previously fixed. nofix: there are no plans to fix this erratum. eval: plans to fix this erratum are under evaluation. row change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.
87C196LB specification update 273002-004 november, 1998 5 of 16 errata no. steppings page status errata a b c 1 x x x 7 nofix j1850 transmitter stall upon bus short 2 x x x 8 nofix executing routines in the users rom while the device is operating in serial programming mode 3 x x x 9 nofix design consideration: non bonded out port pin logic 4 x x x 11 nofix rstsrc register functionality specification changes no. steppings page status specification changes a b c 1 x 12 doc ac characteristicsCtable 9 specification clarifications no. steppings page status specification clarifications a b c none for this revision of the specification update. documentation changes no. document revision page status documentation changes 1 272973-001 14 doc page 6-1, figure 6-1 2 272973-001 14 doc page 6-2, figure 6-3 3 272973-002 14 doc page 2-5, section 2.4, paragaph 1 4 272973-002 15 doc page 2-6, figure 2-5
87C196LB specification update 6 of 16 november, 1998 273002-004 identification information markings 87C196LB processors may be identified electrically according to device type and stepping. refer to the data sheet for instructions on how to obtain the identifier number.
87C196LB specification update 273002-004 november, 1998 7 of 16 errata 1. j1850 transmitter stall upon bus short problem: under certain fault conditions during the transmission of a j1850 message byte, it is possible that the j1850 transmitter state machine may stall resulting in immediate termination of a transmission in progress. under this condition, further message transmissions from the j1850 module are prohibited until the transmit state machine is reset, either by outside message activity or the execution of a software workaround. this problem is typically encountered when the j1850 module is transmitting and a bus short to either vss or vcc occurs on the j1850 bus. a bus short is a fault condition, which under typical operation should not occur. an abrupt stall of the j1850 module during trans- mission of a message frame is typically seen as an error condition by other nodes on the network. external stimulation, such as reception of a message transmitted by another node, or the execution of the software workaround will reset the j1850 transmit state ma- chine. in the event of a j1850 transmitter stall, a software workaround may be executed in the ab- sence of external stimuli to reset the j1850 transmit state machine. execution of the workaround unlocks the j1850 transmitter from a stalled condition. the following workarounds must be executed to guarantee self recovery from a transmit state machine stall. case 1 : upon a transmit error (bit 0, j1850_stat register = 1). 1. set the abort bit in j1850_cmd register; write data 10h. 2. clear the abort bit in the j1850_cmd register; write data 00h. 3. overflow the j1850_tx buffer; write same data (ex. 00h) three times to force overflow condition. 4. set the abort bit in the j1850_cmd register; write data 10h. case 2 : prior to a message transmission. 1. set the abort bit in j1850_cmd register; write data 10h. 2. clear the abort bit in the j1850_cmd register; write data 00h. 3. overflow the j1850_tx buffer; write same data (ex. 00h) three times to force overflow condition. 4. set the abort bit in the j1850_cmd register; write data 1xh (where x is a non-zero value less than 8h.)
87C196LB specification update 8 of 16 november, 1998 273002-004 the two implementations of the software workaround are similar except for the last value written to the command register. the write to the j1850_cmd register does two things, setting of the abort bit and writing a value to the j1850 msg bits. the value written to the j1850 msg bits changes, as noted above, depending on the condition under which the workaround is implemented. this change is necessary to prevent extra invalid symbols from being transmitted on the j1850 bus. the above sequences of commands reset the j1850 transmit state machine and enable immediate transmission of a new message. note: the three successive writes to the j1850_tx buffer will create an overflow condition and result in a j1850_stat interrupt. the overflow interrupt occurs immediately after writing the third byte to the j1850_tx register, the user software must be prepared to handle overflow conditions as a result of executing the software workaround. status: nofix . refer to the summary table of changes to determine the affected stepping(s). 2. executing routines in the users rom while the device is operating in serial programming mode problem: all code fetches above the first 8k bytes of user rom while the device is operating in serial port programming mode will be directed to external memory. therefore, if the user wants to call any routines in the user rom, the entire routine must be within the first 8k bytes of memory (0a000 C 0bfffh in serial port programming mode). for example, if the rism go command is used with a target address of 0c000h, the device will attempt to fetch code from external memory rather than the on-board rom. implication: this errata only affects code fetches from the user rom. data fetches to the entire rom work correctly. it is not possible to execute code from above the first 8k byte of user rom while the device is operating in serial port programming mode. workaround: none. status: nofix . refer to the summary table of changes to determine the affected stepping(s).
87C196LB specification update 273002-004 november, 1998 9 of 16 3. design consideration: non bonded out port pin logic problem: the 87C196LB contains one input only and six i/o ports, port 0 through port 6. each of these seven ports consists of eight-bits, and may function as lsio or special function. the controller is available only in 52ld plcc packaging, constraining the total i/o, and limiting the number of available port pins on any given port. when programming the lb micro, the user software must ensure that values contained in unused bits of the port registers are not relied upon for any operation, such as a conditional branch or jump instruction. these bits should be masked off in the user software. port 0: port 0 is an eight-bit port with shared functionality between the analog to digital converter (sfr) and a high impedance input only port. there are six port 0 pins bonded out, p0.2 through p0.7. the p0.0 and p0.1 pins are not bonded out and the analog inputs for these two channels at the multiplexer are tied to v ref . therefore, initiating a conversion on ach1 results in a value equal to full scale (3ffh). the digital inputs for these two channels are tied to ground, therefore reading p0.0 or p0.1 results in a digital 0. however, it is recommended that the user software not rely on the value read from the p0.0 or p0.1 bit locations for any operation. port 1: port 1 is an eight-bit port with shared functionality between the epa (event processor array) and a low speed input/output (lsio) port. there are four port 1 pins bonded out, p1.0 through p1.3. the p1.4 through p1.7 pins have been removed from the device and is not available to the programmer. corresponding bits in the port registers have been hard-wired to provide the following results when read. however, it is recommended that the user software not rely on the value read from the p1.4 through p1.7 registers for any operations. port 2: port 2 is an eight-bit port with shared functionality between multiple sfr function and a low speed input/output (lsio) port. port 2 has six of the eight pins bonded out, p2.0 through p2.2, p2.4 and p2.6, p2.7. p2.3 and p2.5 have been removed from the device and are not available to the programmer. corresponding bits in the port registers have been hard-wired register bits when read p1_pin.x (x = 4,5,6,7) 1 p1_reg.x (x = 4,5,6,7) 1 p1_dir.x (x = 4,5,6,7) 1 p1_mode.x (x = 4,5,6,7) 0
87C196LB specification update 10 of 16 november, 1998 273002-004 to provide the following results when read. however, it is recommended that the user software not rely on the value read from the p2.3 and p2.5 registers for any operations. port 3, port 4: port 3 and port 4 are eight-bit, bidirectional, memory-mapped i/o ports. they can be addressed only with indirect or indexed addressing and cannot be windowed. ports 3 and 4 provide the multiplexed address/data bus. in programming modes, ports 3 and 4 serve as the programming bus (pbus). port 3 and 4 can also serve as lsio when executing from internal memory. the entire port 3 and port 4 logic exists on the lb micro. port 5: port 5 is an eight-bit, bidirectional port which can be configured to supply the bus-control signals (for external operation) or lsio when running from internal memory. the lb micro has three port 5 pins available, p5.0, p5.2 and p5.3. the remaining port 5 pins, p5.1, p5.4 through p5.7 are not bonded out in the 52ld package, however, the port logic associated with these port 5 bits remains. it is important that the users software does not rely on values contained in the non-bonded port 5 bits. the value in these bit locations may be undefined after power-up reset, and thus the user software must not rely on these bit locations for any device operation. port 6: port 6 is an eight-bit, bidirectional port which can be configured for special function (ssio, epa) or to operate as lsio. six of the port 6 pins are bonded out in the 52ld package, p6.0, p6.1 and p6.4 through p6.7. the remaining two pins, p6.2 and p6.3 have been removed from the device and are not available to the programmer. corresponding bits in the port registers have been hard-wired to provide the following results when read. however, it is recommended that the user software not rely on the value read from the p6.2 and p6.3 registers for any operations. register bits when read p2_pin.x (x = 3,5) 1 p2_reg.x (x = 3,5) 1 p2_dir.x (x = 3,5) 1 p2_mode.x (x = 3,5) 0 register bits when read p6_pin.x (x = 2,3) 1 p6_reg.x (x = 2,3) 1 p6_dir.x (x = 2,3) 1 p6_mode.x (x = 2,3) 0
87C196LB specification update 273002-004 november, 1998 11 of 16 implication: failure to abide by the above may result in unpredictable operation of the users software. workaround: as described above. status: nofix . refer to the summary table of changes to determine the affected stepping(s). 4. rstsrc register functionality problem: the rstsrc register was designed to be initialized to 00h on a v cc power-up condition. however, due to a product erratum, the rstsrc register may not be initialized to 00h on a v cc power-up condition. as a result, the state of the rstsrc register on a v cc power-up condition is indeterminate. implication: applications that rely on the rstsrc register to be 00h on v cc power-up may be adversely affected. status: nofix . refer to the summary table of changes to determine the affected stepping(s).
87C196LB specification update 12 of 16 november, 1998 273002-004 specification changes 1. ac characteristicsCtable 9 issue: four ac parameters have been changed as follows: ?old t chcl max = t + 20 ns t cllh min = -10 ns t rlcl min = 0 ns t clwl min = -5 ns ?new t chcl max = t + 25 ns t cllh min = -15 ns t rlcl min = -5 ns t clwl min = -10 ns affected documents: 87C196LB-20 mhz chmos 16-bit microcontroller datasheet (order number 272807)
87C196LB specification update 273002-004 november, 1998 13 of 16 specification clarifications none for this revision of the specification update.
87C196LB specification update 14 of 16 november, 1998 273002-004 documentation changes 1. page 6-1, figure 6-1 issue: ssio0-clk register address is incorrect. the ssio0-clk address should be 1fb5h. ?old address: 1f95h ?new address: 1fb5h affected documents: 8xc196lx supplement to 8xc196kx, 8xc196jx, 87c196ca users manual (order number 272973) 2. page 6-2, figure 6-3 issue: ssio1-clk register address is incorrect. the ssio1-clk address should be 1fb7h. ?old address: 1f97h ?new address: 1fb7h affected documents: 8xc196lx supplement to 8xc196kx, 8xc196jx, 87c196ca users manual (order number 272973) 3. page 2-5, section 2.4, paragaph 1 problem: description of clkout frequencies in paragraph 1 of section 2.4 is incorrect. ?old 2.4 external timing you can control the output frequency on the clkout pin by programming two uneraseable prom bits. figure 2-5 illustrates the read-only usfr1, which reflects the state of the uneraseable prom bits. you can select from one of three frequencies: f/2, f/4, or f/8. as figure 2-2 on page 2-3 shows, the configurable divider accepts the outputs of the clock generators (f/2) and further divides the frequency to produce the desired output frequency. the clk1:0 bits control the divisor (divide f/2 by either 1, 2, or 4).
87C196LB specification update 273002-004 november, 1998 15 of 16 ?new 2.4 external timing you can control the output frequency on the clkout pin by programming two uneraseable prom bits. figure 2-5 illustrates the read-only usfr1, which reflects the state of the uneraseable prom bits. you can select from one of three frequencies: f, f/2, or f/4. as figure 2-2 on page 2-3 shows, the configurable divider accepts the outputs of the clock generators (f/2) and further divides (or multiplies) the frequency to produce the desired output frequency. the clk1:0 bits control the divisor (divide f/2 by either 1/2, 1, or 2). affected documents: 8xc196lx supplement to 8xc196kx, 8xc196jx, 87c196ca users manual (order number 272973) 4. page 2-6, figure 2-5 problem: the clkout frequencies listed in the figure are incorrect. ?old ?new affected documents: 8xc196lx supplement to 8xc196kx, 8xc196jx, 87c196ca users manual (order number 272973) clk1 clk2 0 0 divide by 1 (clkout=f/2) 0 1 divide by 2 (clkout=f/4) 1 0 divide by 4 (clkout=f/8) 1 1 divide by 1 (clkout=f/2) clk1 clk2 0 0 divide by 1 (clkout=f/2) 0 1 multiply by 2 (clkout=f) 1 0 divide by 2 (clkout=f/4) 1 1 divide by 1 (clkout=f/2)

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